Let's talk about SIDs, baby
Welcome, SID enthusiasts! I have already shared recordings on my YouTube channel ( https://www.youtube.com/@sidemu ), but now I would like to share some technical information about the SIDemu board itself. .: How the SIDemu's sub-sampler works :. Output audio samples are generated every 20th PHI2 clock cycle, which means a mixing frequency of ~49KHz for a PAL system C64. One might think that this would not sound as good as an FPGA implementation, which generates an output audio sample for every PHI2 clock cycle, but let me explain a little more about what actually happens on the SIDemu: In fact, SIDemu does not omit any waveform generator audio samples from the final audio output, it just generates a precisely down-sampled audio sample every 20 PHI2 clocks. The emulation is divided into slices, which are actually PHI2 clock groups. The basic slice size is 20 PHI2 clocks, but in the case of register writes, sub-slices are created, which are added together to form the output audio sa...